Close the stable ABI
Independent command and transition review is the remaining freeze gate.
Evidence, not dates
Build order matters.
Right now
The workload is pinned. Build out execution.
M5 is complete and M6 is active: the first two Conv-SiLU blocks pass through the compiler and runtime. M3/M4 independent review remains required for a stable ABI and final corpus release.
Review conformance
Validate independent fixture derivations and tie the final corpus to the frozen ABI.
Lower the first C2f block
Add 1×1 convolution, split/view, concat liveness, and residual-scale handling for the next block.
Working software →M0–M11
The complete milestone chain.
M6 proceeds against the explicitly pinned M3/M4 candidate. RTL starts after independent review and stable contract freeze; a complete v0 additionally requires the full workload execution path.
M0
Implemented Repository foundation
Structure, build entry points, documentation, CI skeleton, and licensing are tracked.
M1
Implemented Numerical golden model
FP8/INT8 semantics and numerical, layout, activation, and operation tests pass.
M2
Implemented Functional command simulator
Versioned 128-byte command encoding, memory behavior, errors, and simulator tests exist.
M3
In progress Freeze the v0 contract
ABI 0.1 is a candidate. Stable freeze awaits independent command and transition review.
M4
In progress v0 conformance package
46 independent binary fixtures, schema, registry, integrity checks, runner, and CI are implemented.
M5
Implemented Pin + calibrate the first YOLO workload
Artifact, graph, preprocessing, host boundary, FLOAT baseline, INT8 calibration, proxy accuracy, and diagnostics are recorded. Exact target execution belongs to M6.
M6
In progress Minimal compiler + simulated runtime
First two Conv-SiLU blocks pass exactly. Next: C2f branching, whole-model packages, host tail, and layerwise comparisons.
M7
Planned First RTL vertical slice
Decode one command path through INT8 MAC, accumulation, requantization, completion, errors, and differential tests.
M8
Planned Incremental RTL coverage
Add DMA, convolution, and utility operations one conformance-gated step at a time.
M9
Planned FPGA selection + v0 bring-up
Select from measured probes and publish reproducible timing, resources, accuracy, transfers, and latency.
M10
Long-term v1 RISC-V + native FP8
Add only features justified by measured v0 evidence.
M11
Long-term ASIC feasibility + test core
Resolve process, SRAM, IO, clock, power, DFT, verification, packaging, and fabrication collateral.
Non-negotiable
Rules that keep results real.
These controls apply across software, compiler, RTL, FPGA, and eventual silicon.
One source of truth
Opcodes, fields, layouts, error codes, and ABI versions stay aligned across every consumer.
Independent oracles
The golden expectation remains separate from the implementation being tested.
No silent fallback
Unsupported operations, host partitions, errors, saturation, and approximations are declared.
Reproducible evidence
Pin revisions, tools, commands, seeds, artifacts, models, and measurement conditions.
Intermediate comparison
Compare tensors layer by layer instead of trusting only a plausible final detection.
Errors are first-class
Negative cases and illegal states receive the same care as successful execution.