H HASLAB
HASLAB / Build & Fabricate
From software to silicon

Find your starting point.

01 / Start today

Your first build is software.

For students, architecture researchers, and compiler contributors. A computer with Git, Python, and Make is enough to begin with the source-independent tests.

Implemented

Software / reference profile

Study the numerical rules, trace commands through modeled memory, or examine the first two exact Conv-SiLU blocks.

Set up + run the checks →Explore the working slice →

What you can use

  • Python numerical golden model
  • Functional command simulator
  • 46 independent conformance fixtures
  • Calibrated YOLOv8n workload evidence
  • Experimental compiler and simulator runtime for two Conv-SiLU blocks

The real-model experiment additionally needs the pinned export environment, weights, and calibration artifacts. See the setup requirements.

02 / Prepare for hardware

FPGA comes in stages.

No board or bitstream is available yet. v0 establishes a small, measured implementation; v1 explores additions supported by that evidence.

Planned

v0 FPGA core

The first hardware target.

Best fit
University labs and first hardware bring-up.
Planned scope
Host control, INT8/INT32 compute, small local memories, and serialized DMA.
What unlocks it
Reviewed contracts, verified RTL, a complete compiler/runtime path, and resource probes that inform board selection.
See the v0 milestone →
Long-term

v1 FPGA subsystem

A measured expansion of v0.

Best fit
Accelerator and robotics researchers.
Possible scope
RISC-V control, native FP8 evaluation, wider DMA/vector support, and bounded overlap.
What unlocks it
A stable, measured v0 showing which features improve real workloads.
See the v1 research gate →

Want to contribute before boards are selected? Start with contract review, verification, or compiler scheduling.

03 / Explore fabrication

Two scales of silicon.

Both ASIC profiles are long-term research directions. Their eventual configuration depends on measured workloads, the fabrication process, and available memories.

Long-term

Basic ASIC test core

Small, observable, and portable.

Best fit
Open-silicon courses and shared fabrication runs.
Possible scope
A proven compute core, process-specific SRAM, a simple host interface, and scan/self-test support.
Design priority
Make the core easy to inspect and validate within process and shuttle limits.
Follow ASIC feasibility →
Long-term

Integrated edge ASIC

Sized for a complete workload.

Best fit
Advanced research groups and applied laboratories.
Possible scope
Workload-sized compute and SRAM, control, vector utilities, and a viable external-memory interface.
Design priority
Use measured bandwidth, area, and power evidence to choose the integration scope.
Explore the architecture →